In computer architecture, Dynamic Voltage and Frequency Scaling (DVFS) is a power optimization technique in which a processor or other integrated circuit component can be made to work at different frequency and voltage settings, depending on real-time performance and/or power requirements. Conventional DVFS solutions are characterized by the ability to adjust a frequency and voltage of a processor or microprocessor dynamically, either to conserve or optimize power or to reduce the amount of heat generated by the chip. In traditional DVFS schemes, manufacturers often impose safety limits to one or more settings during operation. For example, for any given voltage level, a maximum frequency that corresponds to a safe operating range may be imposed to limit the potential for component malfunction and/or prevent the risk of premature failure—due to overheating, for example.
Typically, these limits are calculated with built-in margins that account for process variations that may arise from a variety of different sources such as integrated circuit process variations, random noise (e.g., voltage fluctuations), temperature variations, age-related degradation, and/or voltage regulator tolerances, etc. While reasonably effective to prevent overheating due to excessive voltages or operating frequencies, these margins also decrease the overall power efficiency of the chip, since the margins are often over-budgeted to account for worst-case scenarios. For instance, software may request a particular clock frequency for a microprocessor and a larger voltage is assigned than is optimally required to operate the microprocessor at that frequency, to account for the margin.
Recently, new solutions have been introduced that attempt to solve this issue. One such proposed solution uses a noise-aware phase locked loop (NAPLL) that accounts for noise and voltage regulator margins of an integrated circuit but fails to account for any other factors that potentially contribute to inefficiencies. As such, margins must still be built-in to account for those factors that decrease the power efficiency of the integrated circuit, or else expose users to the risks inherent to overheating. Another proposed solution is to use a closed loop DVFS scheme that uses a digital ring oscillator as the clock generator. However, digital ring oscillators can themselves suffer from process variations and need additional margining. Each of these schemes also suffer from a lack of scalability, since the number of clock domains that are part of the same voltage rail is inherently limited.